adc.h — Maple v0.0.12 Documentation

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# `adc.h`

Analog to Digital Conversion (ADC) support.

Contents

- Types
- Devices
- Functions
- Register Map Base Pointers
- Register Bit Definitions
  - Status register
  - Control register 1
  - Control register 2
  - Sample time register 1
  - Sample time register 2
  - Injected channel data offset register
  - Watchdog high threshold register
  - Watchdog low threshold register
  - Regular sequence register 1
  - Regular sequence register 2
  - Regular sequence register 3
  - Injected sequence register
  - Injected data registers
  - Regular data register

## Types

struct adc_dev

> ADC device type.

> Public Members

> > adc_reg_map * regs

> >   Register map.

> > rcc_clk_id clk_id

> >   RCC clock information.

struct adc_reg_map

> ADC register map type.

> Public Members

> > __io uint32 SR

> >   Status register.

> > __io uint32 CR1

> >   Control register 1.

> > __io uint32 CR2

> >   Control register 2.

> > __io uint32 SMPR1

> >   Sample time register 1.

> > __io uint32 SMPR2

> >   Sample time register 2.

> > __io uint32 JOFR1

> >   Injected channel data offset register 1.

> > __io uint32 JOFR2

> >   Injected channel data offset register 2.

> > __io uint32 JOFR3

> >   Injected channel data offset register 3.

> > __io uint32 JOFR4

> >   Injected channel data offset register 4.

> > __io uint32 HTR

> >   Watchdog high threshold register.

> > __io uint32 LTR

> >   Watchdog low threshold register.

> > __io uint32 SQR1

> >   Regular sequence register 1.

> > __io uint32 SQR2

> >   Regular sequence register 2.

> > __io uint32 SQR3

> >   Regular sequence register 3.

> > __io uint32 JSQR

> >   Injected sequence register.

> > __io uint32 JDR1

> >   Injected data register 1.

> > __io uint32 JDR2

> >   Injected data register 2.

> > __io uint32 JDR3

> >   Injected data register 3.

> > __io uint32 JDR4

> >   Injected data register 4.

> > __io uint32 DR

> >   Regular data register.

adc_extsel_event enum

  External event selector for regular group conversion.

  See: | adc_set_extsel

  Values:

  - `ADC_ADC12_TIM1_CC1``= (0 << 17)` -

    ADC1 and ADC2: Timer 1 CC1 event.

  - `ADC_ADC12_TIM1_CC2``= (1 << 17)` -

    ADC1 and ADC2: Timer 1 CC2 event.

  - `ADC_ADC12_TIM1_CC3``= (2 << 17)` -

    ADC1 and ADC2: Timer 1 CC3 event.

  - `ADC_ADC12_TIM2_CC2``= (3 << 17)` -

    ADC1 and ADC2: Timer 2 CC2 event.

  - `ADC_ADC12_TIM3_TRGO``= (4 << 17)` -

    ADC1 and ADC2: Timer 3 TRGO event.

  - `ADC_ADC12_TIM4_CC4``= (5 << 17)` -

    ADC1 and ADC2: Timer 4 CC4 event.

  - `ADC_ADC12_EXTI11``= (6 << 17)` -

    ADC1 and ADC2: EXTI11 event.

  - `ADC_ADC12_TIM8_TRGO``= (6 << 17)` -

    ADC1 and ADC2: Timer 8 TRGO event (high density only).

  - `ADC_ADC12_SWSTART``= (7 << 17)` -

    ADC1 and ADC2: Software start.

  - `ADC_ADC3_TIM3_CC1``= (0 << 17)` -

    ADC3: Timer 3 CC1 event (high density only).

  - `ADC_ADC3_TIM2_CC3``= (1 << 17)` -

    ADC3: Timer 2 CC3 event (high density only).

  - `ADC_ADC3_TIM1_CC3``= (2 << 17)` -

    ADC3: Timer 1 CC3 event (high density only).

  - `ADC_ADC3_TIM8_CC1``= (3 << 17)` -

    ADC3: Timer 8 CC1 event (high density only).

  - `ADC_ADC3_TIM8_TRGO``= (4 << 17)` -

    ADC3: Timer 8 TRGO event (high density only).

  - `ADC_ADC3_TIM5_CC1``= (5 << 17)` -

    ADC3: Timer 5 CC1 event (high density only).

  - `ADC_ADC3_TIM5_CC3``= (6 << 17)` -

    ADC3: Timer 5 CC3 event (high density only).

  - `ADC_ADC3_SWSTART``= (7 << 17)` -

    ADC3: Software start (high density only).

  - `ADC_SWSTART``= (7 << 17)` -

    ADC1, ADC2, ADC3: Software start.

adc_smp_rate enum

  ADC sample times, in ADC clock cycles.

  These control the amount of time spent sampling the input voltage.

  Values:

  - `ADC_SMPR_1_5` -

    1.5 ADC cycles

  - `ADC_SMPR_7_5` -

    7.5 ADC cycles

  - `ADC_SMPR_13_5` -

    13.5 ADC cycles

  - `ADC_SMPR_28_5` -

    28.5 ADC cycles

  - `ADC_SMPR_41_5` -

    41.5 ADC cycles

  - `ADC_SMPR_55_5` -

    55.5 ADC cycles

  - `ADC_SMPR_71_5` -

    71.5 ADC cycles

  - `ADC_SMPR_239_5` -

    239.5 ADC cycles

## Devices

const adc_dev * ADC1

  ADC1 device.

const adc_dev * ADC2

  ADC2 device.

const adc_dev * ADC3

  ADC3 device.

## Functions

void adc_init(const adc_dev * dev)

  Initialize an ADC peripheral.

  Initializes the RCC clock line for the given peripheral. Resets ADC device registers.

  Parameters: | `dev` - ADC peripheral to initialize

void adc_calibrate(const adc_dev * dev)

  Calibrate an ADC peripheral.

  Parameters: | `dev` - adc device

void adc_set_extsel(const adc_dev * dev, adc_extsel_event event)

  Set external event select for regular group.

  Parameters: | `dev` - ADC device `event` - Event used to trigger the start of conversion.
  See: | adc_extsel_event

void adc_enable(const adc_dev * dev)

  Enable an adc peripheral.

  Parameters: | `dev` - ADC device to enable

void adc_disable(const adc_dev * dev)

  Disable an ADC peripheral.

  Parameters: | `dev` - ADC device to disable

void adc_disable_all(void)

  Disable all ADC peripherals.

void adc_foreach(void(*)(const adc_dev *) fn)

  Call a function on all ADC devices.

  Parameters: | `fn` - Function to call on each ADC device.

void adc_set_sample_rate(const adc_dev * dev, adc_smp_rate smp_rate)

  Turn the given sample rate into values for ADC_SMPRx.

  Don’t call this during conversion.

  Parameters: | `dev` - adc device `smp_rate` - sample rate to set
  See: | adc_smp_rate

uint16 adc_read(const adc_dev * dev, uint8 channel)

  Perform a single synchronous software triggered conversion on a channel.

  Parameters: | `dev` - ADC device to use for reading. `channel` - channel to convert
  Return: | conversion result

void adc_set_reg_seqlen(const adc_dev * dev, uint8 length)

  Set the regular channel sequence length.

  Defines the total number of conversions in the regular channel conversion sequence.

  Parameters: | `dev` - ADC device. `length` - Regular channel sequence length, from 1 to 16.

void adc_set_exttrig(const adc_dev * dev, uint8 enable)

  Set external trigger conversion mode event for regular channels.

  Parameters: | `dev` - ADC device `enable` - If 1, conversion on external events is enabled; if 0, disabled.

## Register Map Base Pointers

ADC1_BASE

  ADC1 register map base pointer.

ADC2_BASE

  ADC2 register map base pointer.

ADC3_BASE

  ADC3 register map base pointer.

## Register Bit Definitions

### Status register

ADC_SR_AWD_BIT

ADC_SR_EOC_BIT

ADC_SR_JEOC_BIT

ADC_SR_JSTRT_BIT

ADC_SR_STRT_BIT

ADC_SR_AWD

ADC_SR_EOC

ADC_SR_JEOC

ADC_SR_JSTRT

ADC_SR_STRT

### Control register 1

ADC_CR1_EOCIE_BIT

ADC_CR1_AWDIE_BIT

ADC_CR1_JEOCIE_BIT

ADC_CR1_SCAN_BIT

ADC_CR1_AWDSGL_BIT

ADC_CR1_JAUTO_BIT

ADC_CR1_DISCEN_BIT

ADC_CR1_JDISCEN_BIT

ADC_CR1_JAWDEN_BIT

ADC_CR1_AWDEN_BIT

ADC_CR1_AWDCH

ADC_CR1_EOCIE

ADC_CR1_AWDIE

ADC_CR1_JEOCIE

ADC_CR1_SCAN

ADC_CR1_AWDSGL

ADC_CR1_JAUTO

ADC_CR1_DISCEN

ADC_CR1_JDISCEN

ADC_CR1_DISCNUM

ADC_CR1_JAWDEN

ADC_CR1_AWDEN

### Control register 2

ADC_CR2_ADON_BIT

ADC_CR2_CONT_BIT

ADC_CR2_CAL_BIT

ADC_CR2_RSTCAL_BIT

ADC_CR2_DMA_BIT

ADC_CR2_ALIGN_BIT

ADC_CR2_JEXTTRIG_BIT

ADC_CR2_EXTTRIG_BIT

ADC_CR2_JSWSTART_BIT

ADC_CR2_SWSTART_BIT

ADC_CR2_TSEREFE_BIT

ADC_CR2_ADON

ADC_CR2_CONT

ADC_CR2_CAL

ADC_CR2_RSTCAL

ADC_CR2_DMA

ADC_CR2_ALIGN

ADC_CR2_JEXTSEL

ADC_CR2_JEXTTRIG

ADC_CR2_EXTSEL

ADC_CR2_EXTTRIG

ADC_CR2_JSWSTART

ADC_CR2_SWSTART

ADC_CR2_TSEREFE

### Sample time register 1

ADC_SMPR1_SMP17

ADC_SMPR1_SMP16

ADC_SMPR1_SMP15

ADC_SMPR1_SMP14

ADC_SMPR1_SMP13

ADC_SMPR1_SMP12

ADC_SMPR1_SMP11

ADC_SMPR1_SMP10

### Sample time register 2

ADC_SMPR2_SMP9

ADC_SMPR2_SMP8

ADC_SMPR2_SMP7

ADC_SMPR2_SMP6

ADC_SMPR2_SMP5

ADC_SMPR2_SMP4

ADC_SMPR2_SMP3

ADC_SMPR2_SMP2

ADC_SMPR2_SMP1

ADC_SMPR2_SMP0

### Injected channel data offset register

ADC_JOFR_JOFFSET

### Watchdog high threshold register

ADC_HTR_HT

### Watchdog low threshold register

ADC_LTR_LT

### Regular sequence register 1

ADC_SQR1_L

ADC_SQR1_SQ16

ADC_SQR1_SQ15

ADC_SQR1_SQ14

ADC_SQR1_SQ13

### Regular sequence register 2

ADC_SQR2_SQ12

ADC_SQR2_SQ11

ADC_SQR2_SQ10

ADC_SQR2_SQ9

ADC_SQR2_SQ8

ADC_SQR2_SQ7

### Regular sequence register 3

ADC_SQR3_SQ6

ADC_SQR3_SQ5

ADC_SQR3_SQ4

ADC_SQR3_SQ3

ADC_SQR3_SQ2

ADC_SQR3_SQ1

### Injected sequence register

ADC_JSQR_JL

ADC_JSQR_JL_1CONV

ADC_JSQR_JL_2CONV

ADC_JSQR_JL_3CONV

ADC_JSQR_JL_4CONV

ADC_JSQR_JSQ4

ADC_JSQR_JSQ3

ADC_JSQR_JSQ2

ADC_JSQR_JSQ1

### Injected data registers

ADC_JDR_JDATA

### Regular data register

ADC_DR_ADC2DATA

ADC_DR_DATA

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