fsmc.h — Maple v0.0.12 Documentation

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# `fsmc.h`

Flexible Static Memory Controller (FSMC) support.

Contents

- Types
- Devices
- Functions
- Memory Bank Boundary Addresses
- Register Map Base Pointers
- Register Bit Definitions
  - NOR/PSRAM Chip-Select Control Registers
  - SRAM/NOR-Flash Chip-Select Timing Registers
  - SRAM/NOR-Flash Write Timing Registers
  - NAND Flash/PC Card Controller Registers
  - FIFO Status And Interrupt Registers
  - Common Memory Space Timing Registers
  - Attribute Memory Space Timing Registers
  - I/O Space Timing Register 4

## Types

struct fsmc_reg_map

> FSMC register map type.

> Public Members

> > __io uint32 BCR1

> >   SRAM/NOR-Flash chip-select control register 1.

> > __io uint32 BTR1

> >   SRAM/NOR-Flash chip-select timing register 1.

> > __io uint32 BCR2

> >   SRAM/NOR-Flash chip-select control register 2.

> > __io uint32 BTR2

> >   SRAM/NOR-Flash chip-select timing register 2.

> > __io uint32 BCR3

> >   SRAM/NOR-Flash chip-select control register 3.

> > __io uint32 BTR3

> >   SRAM/NOR-Flash chip-select timing register 3.

> > __io uint32 BCR4

> >   SRAM/NOR-Flash chip-select control register 4.

> > __io uint32 BTR4

> >   SRAM/NOR-Flash chip-select timing register 4.

> > const uint8 RESERVED1[64]

> >   Reserved.

> > __io uint32 PCR2

> >   PC Card/NAND Flash control register 2.

> > __io uint32 SR2

> >   FIFO status and interrupt register 2.

> > __io uint32 PMEM2

> >   Common memory space timing register 2.

> > __io uint32 PATT2

> >   Attribute memory space timing register 2.

> > const uint8 RESERVED2[4]

> >   Reserved.

> > __io uint32 ECCR2

> >   ECC result register 2.

> > const uint8 RESERVED3[2]

> > __io uint32 PCR3

> >   PC Card/NAND Flash control register 3.

> > __io uint32 SR3

> >   FIFO status and interrupt register 3.

> > __io uint32 PMEM3

> >   Common memory space timing register 3.

> > __io uint32 PATT3

> >   Attribute memory space timing register 3.

> > const uint32 RESERVED4

> >   Reserved.

> > __io uint32 ECCR3

> >   ECC result register 3.

> > const uint8 RESERVED5[8]

> >   Reserved.

> > __io uint32 PCR4

> >   PC Card/NAND Flash control register 4.

> > __io uint32 SR4

> >   FIFO status and interrupt register 4.

> > __io uint32 PMEM4

> >   Common memory space timing register 4.

> > __io uint32 PATT4

> >   Attribute memory space timing register 4.

> > __io uint32 PIO4

> >   I/O space timing register 4.

> > const uint8 RESERVED6[80]

> >   Reserved.

> > __io uint32 BWTR1

> >   SRAM/NOR-Flash write timing register 1.

> > const uint32 RESERVED7

> >   Reserved.

> > __io uint32 BWTR2

> >   SRAM/NOR-Flash write timing register 2.

> > const uint32 RESERVED8

> >   Reserved.

> > __io uint32 BWTR3

> >   SRAM/NOR-Flash write timing register 3.

> > const uint32 RESERVED9

> >   Reserved.

> > __io uint32 BWTR4

> >   SRAM/NOR-Flash write timing register 4.

struct fsmc_nor_psram_reg_map

> FSMC NOR/PSRAM register map type.

> Public Members

> > __io uint32 BCR

> >   Chip-select control register.

> > __io uint32 BTR

> >   Chip-select timing register.

> > const uint8 RESERVED[252]

> >   Reserved.

> > __io uint32 BWTR

> >   Write timing register.

## Devices

None at this time.

## Functions

void fsmc_sram_init_gpios(void)

  Configure FSMC GPIOs for use with SRAM.

void fsmc_nor_psram_set_datast(fsmc_nor_psram_reg_map * regs, uint8 datast)

  Set the DATAST bits in the given NOR/PSRAM register map’s chip-select timing register (FSMC_BTR).

  Parameters: | `regs` - NOR Flash/PSRAM register map whose chip-select timing register to set. `datast` - Value to use for DATAST bits.

void fsmc_nor_psram_set_addset(fsmc_nor_psram_reg_map * regs, uint8 addset)

  Set the ADDHLD bits in the given NOR/PSRAM register map’s chip select timing register (FSMC_BTRx).

  Parameters: | `regs` - NOR Flash/PSRAM register map whose chip-select timing register to set. `addset` - Value to use for ADDSET bits.

## Memory Bank Boundary Addresses

FSMC_BANK1

  Pointer to base address of FSMC memory bank 1 (split into 4 regions, each supporting 1 NOR Flash, SRAM, or PSRAM chip).

FSMC_BANK2

  Pointer to base address of FSMC memory bank 2 (for NAND Flash).

FSMC_BANK3

  Pointer to base address of FSMC memory bank 3 (for NAND Flash).

FSMC_BANK4

  Pointer to base address of FSMC memory bank 4 (for PC card devices.

FSMC_NOR_PSRAM_REGION1

  Pointer to base address of FSMC memory bank 1, region 1 (for NOR/PSRAM).

FSMC_NOR_PSRAM_REGION2

  Pointer to base address of FSMC memory bank 1, region 2 (for NOR/PSRAM).

FSMC_NOR_PSRAM_REGION3

  Pointer to base address of FSMC memory bank 1, region 3 (for NOR/PSRAM).

FSMC_NOR_PSRAM_REGION4

  Pointer to base address of FSMC memory bank 1, region 4 (for NOR/PSRAM).

## Register Map Base Pointers

FSMC_BASE

  FSMC register map base pointer.

FSMC_NOR_PSRAM1_BASE

  FSMC NOR/PSRAM base pointer 1.

FSMC_NOR_PSRAM2_BASE

  FSMC NOR/PSRAM base pointer 2.

FSMC_NOR_PSRAM3_BASE

  FSMC NOR/PSRAM base pointer 3.

FSMC_NOR_PSRAM4_BASE

  FSMC NOR/PSRAM base pointer 4.

## Register Bit Definitions

### NOR/PSRAM Chip-Select Control Registers

FSMC_BCR_CBURSTRW_BIT

FSMC_BCR_ASYNCWAIT_BIT

FSMC_BCR_EXTMOD_BIT

FSMC_BCR_WAITEN_BIT

FSMC_BCR_WREN_BIT

FSMC_BCR_WAITCFG_BIT

FSMC_BCR_WRAPMOD_BIT

FSMC_BCR_WAITPOL_BIT

FSMC_BCR_BURSTEN_BIT

FSMC_BCR_FACCEN_BIT

FSMC_BCR_MUXEN_BIT

FSMC_BCR_MBKEN_BIT

FSMC_BCR_CBURSTRW

FSMC_BCR_ASYNCWAIT

FSMC_BCR_EXTMOD

FSMC_BCR_WAITEN

FSMC_BCR_WREN

FSMC_BCR_WAITCFG

FSMC_BCR_WRAPMOD

FSMC_BCR_WAITPOL

FSMC_BCR_BURSTEN

FSMC_BCR_FACCEN

FSMC_BCR_MWID

FSMC_BCR_MWID_8BITS

FSMC_BCR_MWID_16BITS

FSMC_BCR_MTYP

FSMC_BCR_MTYP_SRAM

FSMC_BCR_MTYP_PSRAM

FSMC_BCR_MTYP_NOR_FLASH

FSMC_BCR_MUXEN

FSMC_BCR_MBKEN

### SRAM/NOR-Flash Chip-Select Timing Registers

FSMC_BTR_ACCMOD

FSMC_BTR_ACCMOD_A

FSMC_BTR_ACCMOD_B

FSMC_BTR_ACCMOD_C

FSMC_BTR_ACCMOD_D

FSMC_BTR_DATLAT

FSMC_BTR_CLKDIV

FSMC_BTR_BUSTURN

FSMC_BTR_DATAST

FSMC_BTR_ADDHLD

FSMC_BTR_ADDSET

### SRAM/NOR-Flash Write Timing Registers

FSMC_BWTR_ACCMOD

FSMC_BWTR_ACCMOD_A

FSMC_BWTR_ACCMOD_B

FSMC_BWTR_ACCMOD_C

FSMC_BWTR_ACCMOD_D

FSMC_BWTR_DATLAT

FSMC_BWTR_CLKDIV

FSMC_BWTR_DATAST

FSMC_BWTR_ADDHLD

FSMC_BWTR_ADDSET

### NAND Flash/PC Card Controller Registers

FSMC_PCR_ECCEN_BIT

FSMC_PCR_PTYP_BIT

FSMC_PCR_PBKEN_BIT

FSMC_PCR_PWAITEN_BIT

FSMC_PCR_ECCPS

FSMC_PCR_ECCPS_256B

FSMC_PCR_ECCPS_512B

FSMC_PCR_ECCPS_1024B

FSMC_PCR_ECCPS_2048B

FSMC_PCR_ECCPS_4096B

FSMC_PCR_ECCPS_8192B

FSMC_PCR_TAR

FSMC_PCR_TCLR

FSMC_PCR_ECCEN

FSMC_PCR_PWID

FSMC_PCR_PWID_8BITS

FSMC_PCR_PWID_16BITS

FSMC_PCR_PTYP

FSMC_PCR_PTYP_PC_CF_PCMCIA

FSMC_PCR_PTYP_NAND

FSMC_PCR_PBKEN

FSMC_PCR_PWAITEN

### FIFO Status And Interrupt Registers

FSMC_SR_FEMPT_BIT

FSMC_SR_IFEN_BIT

FSMC_SR_ILEN_BIT

FSMC_SR_IREN_BIT

FSMC_SR_IFS_BIT

FSMC_SR_ILS_BIT

FSMC_SR_IRS_BIT

FSMC_SR_FEMPT

FSMC_SR_IFEN

FSMC_SR_ILEN

FSMC_SR_IREN

FSMC_SR_IFS

FSMC_SR_ILS

FSMC_SR_IRS

### Common Memory Space Timing Registers

FSMC_PMEM_MEMHIZ

FSMC_PMEM_MEMHOLD

FSMC_PMEM_MEMWAIT

FSMC_PMEM_MEMSET

### Attribute Memory Space Timing Registers

FSMC_PATT_ATTHIZ

FSMC_PATT_ATTHOLD

FSMC_PATT_ATTWAIT

FSMC_PATT_ATTSET

### I/O Space Timing Register 4

FSMC_PIO_IOHIZ

FSMC_PIO_IOHOLD

FSMC_PIO_IOWAIT

FSMC_PIO_IOSET

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