rcc.h — Maple v0.0.12 Documentation

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# `rcc.h`

Reset and Clock Control (RCC) support.

Contents

- Types
- Devices
- Functions
- Register Map Base Pointers
- Register Bit Definitions
  - Clock control register
  - Clock configuration register
  - Clock interrupt register
  - APB2 peripheral reset register
  - APB1 peripheral reset register
  - AHB peripheral clock enable register
  - APB2 peripheral clock enable register
  - APB1 peripheral clock enable register
  - Backup domain control register
  - Control/status register

## Types

struct rcc_reg_map

> RCC register map type.

> Public Members

> > __io uint32 CR

> >   Clock control register.

> > __io uint32 CFGR

> >   Clock configuration register.

> > __io uint32 CIR

> >   Clock interrupt register.

> > __io uint32 APB2RSTR

> >   APB2 peripheral reset register.

> > __io uint32 APB1RSTR

> >   APB1 peripheral reset register.

> > __io uint32 AHBENR

> >   AHB peripheral clock enable register.

> > __io uint32 APB2ENR

> >   APB2 peripheral clock enable register.

> > __io uint32 APB1ENR

> >   APB1 peripheral clock enable register.

> > __io uint32 BDCR

> >   Backup domain control register.

> > __io uint32 CSR

> >   Control/status register.

rcc_sysclk_src enum

  SYSCLK sources.

  See: | rcc_clk_init()

  Values:

  - `RCC_CLKSRC_HSI``= 0x0` -
  - `RCC_CLKSRC_HSE``= 0x1` -
  - `RCC_CLKSRC_PLL``= 0x2` -

rcc_pllsrc enum

  PLL entry clock source.

  See: | rcc_clk_init()

  Values:

  - `RCC_PLLSRC_HSE``= (0x1 << 16)` -
  - `RCC_PLLSRC_HSI_DIV_2``= (0x0 << 16)` -

rcc_pll_multiplier enum

  PLL multipliers.

  See: | rcc_clk_init()

  Values:

  - `RCC_PLLMUL_2``= (0x0 << 18)` -
  - `RCC_PLLMUL_3``= (0x1 << 18)` -
  - `RCC_PLLMUL_4``= (0x2 << 18)` -
  - `RCC_PLLMUL_5``= (0x3 << 18)` -
  - `RCC_PLLMUL_6``= (0x4 << 18)` -
  - `RCC_PLLMUL_7``= (0x5 << 18)` -
  - `RCC_PLLMUL_8``= (0x6 << 18)` -
  - `RCC_PLLMUL_9``= (0x7 << 18)` -
  - `RCC_PLLMUL_10``= (0x8 << 18)` -
  - `RCC_PLLMUL_11``= (0x9 << 18)` -
  - `RCC_PLLMUL_12``= (0xA << 18)` -
  - `RCC_PLLMUL_13``= (0xB << 18)` -
  - `RCC_PLLMUL_14``= (0xC << 18)` -
  - `RCC_PLLMUL_15``= (0xD << 18)` -
  - `RCC_PLLMUL_16``= (0xE << 18)` -

rcc_clk_id enum

  Identifies bus and clock line for a peripheral.

  Also generally useful as a unique identifier for that peripheral (or its corresponding device struct).

  Values:

  - `RCC_GPIOA` -
  - `RCC_GPIOB` -
  - `RCC_GPIOC` -
  - `RCC_GPIOD` -
  - `RCC_AFIO` -
  - `RCC_ADC1` -
  - `RCC_ADC2` -
  - `RCC_ADC3` -
  - `RCC_USART1` -
  - `RCC_USART2` -
  - `RCC_USART3` -
  - `RCC_TIMER1` -
  - `RCC_TIMER2` -
  - `RCC_TIMER3` -
  - `RCC_TIMER4` -
  - `RCC_SPI1` -
  - `RCC_SPI2` -
  - `RCC_DMA1` -
  - `RCC_PWR` -
  - `RCC_BKP` -
  - `RCC_I2C1` -
  - `RCC_I2C2` -
  - `RCC_CRC` -
  - `RCC_FLITF` -
  - `RCC_SRAM` -
  - `RCC_GPIOE` -
  - `RCC_GPIOF` -
  - `RCC_GPIOG` -
  - `RCC_UART4` -
  - `RCC_UART5` -
  - `RCC_TIMER5` -
  - `RCC_TIMER6` -
  - `RCC_TIMER7` -
  - `RCC_TIMER8` -
  - `RCC_FSMC` -
  - `RCC_DAC` -
  - `RCC_DMA2` -
  - `RCC_SDIO` -
  - `RCC_SPI3` -
  - `RCC_TIMER9` -
  - `RCC_TIMER10` -
  - `RCC_TIMER11` -
  - `RCC_TIMER12` -
  - `RCC_TIMER13` -
  - `RCC_TIMER14` -

rcc_clk_domain enum

  Values:

  - `RCC_APB1` -
  - `RCC_APB2` -
  - `RCC_AHB` -

rcc_prescaler enum

  Prescaler identifiers.

  See: | rcc_set_prescaler()

  Values:

  - `RCC_PRESCALER_AHB` -
  - `RCC_PRESCALER_APB1` -
  - `RCC_PRESCALER_APB2` -
  - `RCC_PRESCALER_USB` -
  - `RCC_PRESCALER_ADC` -

rcc_adc_divider enum

  ADC prescaler dividers.

  See: | rcc_set_prescaler()

  Values:

  - `RCC_ADCPRE_PCLK_DIV_2``= 0x0 << 14` -
  - `RCC_ADCPRE_PCLK_DIV_4``= 0x1 << 14` -
  - `RCC_ADCPRE_PCLK_DIV_6``= 0x2 << 14` -
  - `RCC_ADCPRE_PCLK_DIV_8``= 0x3 << 14` -

rcc_apb1_divider enum

  APB1 prescaler dividers.

  See: | rcc_set_prescaler()

  Values:

  - `RCC_APB1_HCLK_DIV_1``= 0x0 << 8` -
  - `RCC_APB1_HCLK_DIV_2``= 0x4 << 8` -
  - `RCC_APB1_HCLK_DIV_4``= 0x5 << 8` -
  - `RCC_APB1_HCLK_DIV_8``= 0x6 << 8` -
  - `RCC_APB1_HCLK_DIV_16``= 0x7 << 8` -

rcc_apb2_divider enum

  APB2 prescaler dividers.

  See: | rcc_set_prescaler()

  Values:

  - `RCC_APB2_HCLK_DIV_1``= 0x0 << 11` -
  - `RCC_APB2_HCLK_DIV_2``= 0x4 << 11` -
  - `RCC_APB2_HCLK_DIV_4``= 0x5 << 11` -
  - `RCC_APB2_HCLK_DIV_8``= 0x6 << 11` -
  - `RCC_APB2_HCLK_DIV_16``= 0x7 << 11` -

rcc_ahb_divider enum

  AHB prescaler dividers.

  See: | rcc_set_prescaler()

  Values:

  - `RCC_AHB_SYSCLK_DIV_1``= 0x0 << 4` -
  - `RCC_AHB_SYSCLK_DIV_2``= 0x8 << 4` -
  - `RCC_AHB_SYSCLK_DIV_4``= 0x9 << 4` -
  - `RCC_AHB_SYSCLK_DIV_8``= 0xA << 4` -
  - `RCC_AHB_SYSCLK_DIV_16``= 0xB << 4` -
  - `RCC_AHB_SYSCLK_DIV_32``= 0xC << 4` -
  - `RCC_AHB_SYSCLK_DIV_64``= 0xD << 4` -
  - `RCC_AHB_SYSCLK_DIV_128``= 0xD << 4` -
  - `RCC_AHB_SYSCLK_DIV_256``= 0xE << 4` -
  - `RCC_AHB_SYSCLK_DIV_512``= 0xF << 4` -

## Devices

None.

## Functions

void rcc_clk_init(rcc_sysclk_src sysclk_src, rcc_pllsrc pll_src, rcc_pll_multiplier pll_mul)

  Initialize the clock control system.

  Initializes the system clock source to use the PLL driven by an external oscillator

  Parameters: | `sysclk_src` - system clock source, must be PLL `pll_src` - pll clock source, must be HSE `pll_mul` - pll multiplier

void rcc_clk_enable(rcc_clk_id id)

  Turn on the clock line on a peripheral.

  Parameters: | `id` - Clock ID of the peripheral to turn on.

void rcc_reset_dev(rcc_clk_id id)

  Reset a peripheral.

  Parameters: | `id` - Clock ID of the peripheral to reset.

rcc_clk_domain rcc_dev_clk(rcc_clk_id id)

  Get a peripheral’s clock domain.

  Parameters: | `id` - Clock ID of the peripheral whose clock domain to return
  Return: | Clock source for the given clock ID

void rcc_set_prescaler(rcc_prescaler prescaler, uint32 divider)

  Set the divider on a peripheral prescaler.

  Parameters: | `prescaler` - prescaler to set `divider` - prescaler divider

## Register Map Base Pointers

RCC_BASE

  RCC register map base pointer.

## Register Bit Definitions

### Clock control register

RCC_CR_PLLRDY_BIT

RCC_CR_PLLON_BIT

RCC_CR_CSSON_BIT

RCC_CR_HSEBYP_BIT

RCC_CR_HSERDY_BIT

RCC_CR_HSEON_BIT

RCC_CR_HSIRDY_BIT

RCC_CR_HSION_BIT

RCC_CR_PLLRDY

RCC_CR_PLLON

RCC_CR_CSSON

RCC_CR_HSEBYP

RCC_CR_HSERDY

RCC_CR_HSEON

RCC_CR_HSICAL

RCC_CR_HSITRIM

RCC_CR_HSIRDY

RCC_CR_HSION

### Clock configuration register

RCC_CFGR_USBPRE_BIT

RCC_CFGR_PLLXTPRE_BIT

RCC_CFGR_PLLSRC_BIT

RCC_CFGR_MCO

RCC_CFGR_USBPRE

RCC_CFGR_PLLMUL

RCC_CFGR_PLLXTPRE

RCC_CFGR_PLLSRC

RCC_CFGR_ADCPRE

RCC_CFGR_PPRE2

RCC_CFGR_PPRE1

RCC_CFGR_HPRE

RCC_CFGR_SWS

RCC_CFGR_SWS_PLL

RCC_CFGR_SWS_HSE

RCC_CFGR_SW

RCC_CFGR_SW_PLL

RCC_CFGR_SW_HSE

### Clock interrupt register

RCC_CIR_CSSC_BIT

RCC_CIR_PLLRDYC_BIT

RCC_CIR_HSERDYC_BIT

RCC_CIR_HSIRDYC_BIT

RCC_CIR_LSERDYC_BIT

RCC_CIR_LSIRDYC_BIT

RCC_CIR_PLLRDYIE_BIT

RCC_CIR_HSERDYIE_BIT

RCC_CIR_HSIRDYIE_BIT

RCC_CIR_LSERDYIE_BIT

RCC_CIR_LSIRDYIE_BIT

RCC_CIR_CSSF_BIT

RCC_CIR_PLLRDYF_BIT

RCC_CIR_HSERDYF_BIT

RCC_CIR_HSIRDYF_BIT

RCC_CIR_LSERDYF_BIT

RCC_CIR_LSIRDYF_BIT

RCC_CIR_CSSC

RCC_CIR_PLLRDYC

RCC_CIR_HSERDYC

RCC_CIR_HSIRDYC

RCC_CIR_LSERDYC

RCC_CIR_LSIRDYC

RCC_CIR_PLLRDYIE

RCC_CIR_HSERDYIE

RCC_CIR_HSIRDYIE

RCC_CIR_LSERDYIE

RCC_CIR_LSIRDYIE

RCC_CIR_CSSF

RCC_CIR_PLLRDYF

RCC_CIR_HSERDYF

RCC_CIR_HSIRDYF

RCC_CIR_LSERDYF

RCC_CIR_LSIRDYF

### APB2 peripheral reset register

RCC_APB2RSTR_TIM11RST_BIT

RCC_APB2RSTR_TIM10RST_BIT

RCC_APB2RSTR_TIM9RST_BIT

RCC_APB2RSTR_ADC3RST_BIT

RCC_APB2RSTR_USART1RST_BIT

RCC_APB2RSTR_TIM8RST_BIT

RCC_APB2RSTR_SPI1RST_BIT

RCC_APB2RSTR_TIM1RST_BIT

RCC_APB2RSTR_ADC2RST_BIT

RCC_APB2RSTR_ADC1RST_BIT

RCC_APB2RSTR_IOPGRST_BIT

RCC_APB2RSTR_IOPFRST_BIT

RCC_APB2RSTR_IOPERST_BIT

RCC_APB2RSTR_IOPDRST_BIT

RCC_APB2RSTR_IOPCRST_BIT

RCC_APB2RSTR_IOPBRST_BIT

RCC_APB2RSTR_IOPARST_BIT

RCC_APB2RSTR_AFIORST_BIT

RCC_APB2RSTR_TIM11RST

RCC_APB2RSTR_TIM10RST

RCC_APB2RSTR_TIM9RST

RCC_APB2RSTR_ADC3RST

RCC_APB2RSTR_USART1RST

RCC_APB2RSTR_TIM8RST

RCC_APB2RSTR_SPI1RST

RCC_APB2RSTR_TIM1RST

RCC_APB2RSTR_ADC2RST

RCC_APB2RSTR_ADC1RST

RCC_APB2RSTR_IOPGRST

RCC_APB2RSTR_IOPFRST

RCC_APB2RSTR_IOPERST

RCC_APB2RSTR_IOPDRST

RCC_APB2RSTR_IOPCRST

RCC_APB2RSTR_IOPBRST

RCC_APB2RSTR_IOPARST

RCC_APB2RSTR_AFIORST

### APB1 peripheral reset register

RCC_APB1RSTR_DACRST_BIT

RCC_APB1RSTR_PWRRST_BIT

RCC_APB1RSTR_BKPRST_BIT

RCC_APB1RSTR_CANRST_BIT

RCC_APB1RSTR_USBRST_BIT

RCC_APB1RSTR_I2C2RST_BIT

RCC_APB1RSTR_I2C1RST_BIT

RCC_APB1RSTR_UART5RST_BIT

RCC_APB1RSTR_UART4RST_BIT

RCC_APB1RSTR_USART3RST_BIT

RCC_APB1RSTR_USART2RST_BIT

RCC_APB1RSTR_SPI3RST_BIT

RCC_APB1RSTR_SPI2RST_BIT

RCC_APB1RSTR_WWDRST_BIT

RCC_APB1RSTR_TIM14RST_BIT

RCC_APB1RSTR_TIM13RST_BIT

RCC_APB1RSTR_TIM12RST_BIT

RCC_APB1RSTR_TIM7RST_BIT

RCC_APB1RSTR_TIM6RST_BIT

RCC_APB1RSTR_TIM5RST_BIT

RCC_APB1RSTR_TIM4RST_BIT

RCC_APB1RSTR_TIM3RST_BIT

RCC_APB1RSTR_TIM2RST_BIT

RCC_APB1RSTR_DACRST

RCC_APB1RSTR_PWRRST

RCC_APB1RSTR_BKPRST

RCC_APB1RSTR_CANRST

RCC_APB1RSTR_USBRST

RCC_APB1RSTR_I2C2RST

RCC_APB1RSTR_I2C1RST

RCC_APB1RSTR_UART5RST

RCC_APB1RSTR_UART4RST

RCC_APB1RSTR_USART3RST

RCC_APB1RSTR_USART2RST

RCC_APB1RSTR_SPI3RST

RCC_APB1RSTR_SPI2RST

RCC_APB1RSTR_WWDRST

RCC_APB1RSTR_TIM14RST

RCC_APB1RSTR_TIM13RST

RCC_APB1RSTR_TIM12RST

RCC_APB1RSTR_TIM7RST

RCC_APB1RSTR_TIM6RST

RCC_APB1RSTR_TIM5RST

RCC_APB1RSTR_TIM4RST

RCC_APB1RSTR_TIM3RST

RCC_APB1RSTR_TIM2RST

### AHB peripheral clock enable register

RCC_AHBENR_SDIOEN_BIT

RCC_AHBENR_FSMCEN_BIT

RCC_AHBENR_CRCEN_BIT

RCC_AHBENR_FLITFEN_BIT

RCC_AHBENR_SRAMEN_BIT

RCC_AHBENR_DMA2EN_BIT

RCC_AHBENR_DMA1EN_BIT

RCC_AHBENR_SDIOEN

RCC_AHBENR_FSMCEN

RCC_AHBENR_CRCEN

RCC_AHBENR_FLITFEN

RCC_AHBENR_SRAMEN

RCC_AHBENR_DMA2EN

RCC_AHBENR_DMA1EN

### APB2 peripheral clock enable register

RCC_APB2ENR_TIM11EN_BIT

RCC_APB2ENR_TIM10EN_BIT

RCC_APB2ENR_TIM9EN_BIT

RCC_APB2ENR_ADC3EN_BIT

RCC_APB2ENR_USART1EN_BIT

RCC_APB2ENR_TIM8EN_BIT

RCC_APB2ENR_SPI1EN_BIT

RCC_APB2ENR_TIM1EN_BIT

RCC_APB2ENR_ADC2EN_BIT

RCC_APB2ENR_ADC1EN_BIT

RCC_APB2ENR_IOPGEN_BIT

RCC_APB2ENR_IOPFEN_BIT

RCC_APB2ENR_IOPEEN_BIT

RCC_APB2ENR_IOPDEN_BIT

RCC_APB2ENR_IOPCEN_BIT

RCC_APB2ENR_IOPBEN_BIT

RCC_APB2ENR_IOPAEN_BIT

RCC_APB2ENR_AFIOEN_BIT

RCC_APB2ENR_TIM11EN

RCC_APB2ENR_TIM10EN

RCC_APB2ENR_TIM9EN

RCC_APB2ENR_ADC3EN

RCC_APB2ENR_USART1EN

RCC_APB2ENR_TIM8EN

RCC_APB2ENR_SPI1EN

RCC_APB2ENR_TIM1EN

RCC_APB2ENR_ADC2EN

RCC_APB2ENR_ADC1EN

RCC_APB2ENR_IOPGEN

RCC_APB2ENR_IOPFEN

RCC_APB2ENR_IOPEEN

RCC_APB2ENR_IOPDEN

RCC_APB2ENR_IOPCEN

RCC_APB2ENR_IOPBEN

RCC_APB2ENR_IOPAEN

RCC_APB2ENR_AFIOEN

### APB1 peripheral clock enable register

RCC_APB1ENR_DACEN_BIT

RCC_APB1ENR_PWREN_BIT

RCC_APB1ENR_BKPEN_BIT

RCC_APB1ENR_CANEN_BIT

RCC_APB1ENR_USBEN_BIT

RCC_APB1ENR_I2C2EN_BIT

RCC_APB1ENR_I2C1EN_BIT

RCC_APB1ENR_UART5EN_BIT

RCC_APB1ENR_UART4EN_BIT

RCC_APB1ENR_USART3EN_BIT

RCC_APB1ENR_USART2EN_BIT

RCC_APB1ENR_SPI3EN_BIT

RCC_APB1ENR_SPI2EN_BIT

RCC_APB1ENR_WWDEN_BIT

RCC_APB1ENR_TIM14EN_BIT

RCC_APB1ENR_TIM13EN_BIT

RCC_APB1ENR_TIM12EN_BIT

RCC_APB1ENR_TIM7EN_BIT

RCC_APB1ENR_TIM6EN_BIT

RCC_APB1ENR_TIM5EN_BIT

RCC_APB1ENR_TIM4EN_BIT

RCC_APB1ENR_TIM3EN_BIT

RCC_APB1ENR_TIM2EN_BIT

RCC_APB1ENR_DACEN

RCC_APB1ENR_PWREN

RCC_APB1ENR_BKPEN

RCC_APB1ENR_CANEN

RCC_APB1ENR_USBEN

RCC_APB1ENR_I2C2EN

RCC_APB1ENR_I2C1EN

RCC_APB1ENR_UART5EN

RCC_APB1ENR_UART4EN

RCC_APB1ENR_USART3EN

RCC_APB1ENR_USART2EN

RCC_APB1ENR_SPI3EN

RCC_APB1ENR_SPI2EN

RCC_APB1ENR_WWDEN

RCC_APB1ENR_TIM14EN

RCC_APB1ENR_TIM13EN

RCC_APB1ENR_TIM12EN

RCC_APB1ENR_TIM7EN

RCC_APB1ENR_TIM6EN

RCC_APB1ENR_TIM5EN

RCC_APB1ENR_TIM4EN

RCC_APB1ENR_TIM3EN

RCC_APB1ENR_TIM2EN

### Backup domain control register

RCC_BDCR_BDRST_BIT

RCC_BDCR_RTCEN_BIT

RCC_BDCR_LSEBYP_BIT

RCC_BDCR_LSERDY_BIT

RCC_BDCR_LSEON_BIT

RCC_BDCR_BDRST

RCC_BDCR_RTCEN

RCC_BDCR_RTCSEL

RCC_BDCR_RTCSEL_NONE

RCC_BDCR_RTCSEL_LSE

RCC_BDCR_RTCSEL_HSE

RCC_BDCR_LSEBYP

RCC_BDCR_LSERDY

RCC_BDCR_LSEON

### Control/status register

RCC_CSR_LPWRRSTF_BIT

RCC_CSR_WWDGRSTF_BIT

RCC_CSR_IWDGRSTF_BIT

RCC_CSR_SFTRSTF_BIT

RCC_CSR_PORRSTF_BIT

RCC_CSR_PINRSTF_BIT

RCC_CSR_RMVF_BIT

RCC_CSR_LSIRDY_BIT

RCC_CSR_LSION_BIT

RCC_CSR_LPWRRSTF

RCC_CSR_WWDGRSTF

RCC_CSR_IWDGRSTF

RCC_CSR_SFTRSTF

RCC_CSR_PORRSTF

RCC_CSR_PINRSTF

RCC_CSR_RMVF

RCC_CSR_LSIRDY

RCC_CSR_LSION

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