timer.h — Maple v0.0.12 Documentation

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# `timer.h`

Timer support.

Contents

- Types
- Devices
- Functions
  - Enabling and Disabling
  - General Configuration
  - Count and Prescaler
  - Interrupts
  - Capture/Compare
  - DMA
- Register Map Base Pointers
- Register Bit Definitions
  - Control register 1 (CR1)
  - Control register 2 (CR2)
  - Slave mode control register (SMCR)
  - DMA/Interrupt enable register (DIER)
  - Status register (SR)
  - Event generation register (EGR)
  - Capture/compare mode registers, common values
  - Capture/compare mode register 1 (CCMR1)
  - Capture/compare mode register 2 (CCMR2)
  - Capture/compare enable register (CCER)
  - Break and dead-time register (BDTR)
  - DMA control register (DCR)

## Types

The timer register map type, unlike that for most other peripherals in libmaple, is a union rather than a struct. This is due to the fact that there are advanced, general purpose, and basic timers. Thus, each kind of timer has a register map type, and a `union timer_reg_map` ties it all together.

struct timer_adv_reg_map

> Advanced control timer register map type.

> Public Members

> > __io uint32 CR1

> >   Control register 1.

> > __io uint32 CR2

> >   Control register 2.

> > __io uint32 SMCR

> >   Slave mode control register.

> > __io uint32 DIER

> >   DMA/Interrupt enable register.

> > __io uint32 SR

> >   Status register.

> > __io uint32 EGR

> >   Event generation register.

> > __io uint32 CCMR1

> >   Capture/compare mode register 1.

> > __io uint32 CCMR2

> >   Capture/compare mode register 2.

> > __io uint32 CCER

> >   Capture/compare enable register.

> > __io uint32 CNT

> >   Counter.

> > __io uint32 PSC

> >   Prescaler.

> > __io uint32 ARR

> >   Auto-reload register.

> > __io uint32 RCR

> >   Repetition counter register.

> > __io uint32 CCR1

> >   Capture/compare register 1.

> > __io uint32 CCR2

> >   Capture/compare register 2.

> > __io uint32 CCR3

> >   Capture/compare register 3.

> > __io uint32 CCR4

> >   Capture/compare register 4.

> > __io uint32 BDTR

> >   Break and dead-time register.

> > __io uint32 DCR

> >   DMA control register.

> > __io uint32 DMAR

> >   DMA address for full transfer.

struct timer_gen_reg_map

> General purpose timer register map type.

> Public Members

> > __io uint32 CR1

> >   Control register 1.

> > __io uint32 CR2

> >   Control register 2.

> > __io uint32 SMCR

> >   Slave mode control register.

> > __io uint32 DIER

> >   DMA/Interrupt enable register.

> > __io uint32 SR

> >   Status register.

> > __io uint32 EGR

> >   Event generation register.

> > __io uint32 CCMR1

> >   Capture/compare mode register 1.

> > __io uint32 CCMR2

> >   Capture/compare mode register 2.

> > __io uint32 CCER

> >   Capture/compare enable register.

> > __io uint32 CNT

> >   Counter.

> > __io uint32 PSC

> >   Prescaler.

> > __io uint32 ARR

> >   Auto-reload register.

> > const uint32 RESERVED1

> >   Reserved.

> > __io uint32 CCR1

> >   Capture/compare register 1.

> > __io uint32 CCR2

> >   Capture/compare register 2.

> > __io uint32 CCR3

> >   Capture/compare register 3.

> > __io uint32 CCR4

> >   Capture/compare register 4.

> > const uint32 RESERVED2

> >   Reserved.

> > __io uint32 DCR

> >   DMA control register.

> > __io uint32 DMAR

> >   DMA address for full transfer.

struct timer_bas_reg_map

> Basic timer register map type.

> Public Members

> > __io uint32 CR1

> >   Control register 1.

> > __io uint32 CR2

> >   Control register 2.

> > const uint32 RESERVED1

> >   Reserved.

> > __io uint32 DIER

> >   DMA/Interrupt enable register.

> > __io uint32 SR

> >   Status register.

> > __io uint32 EGR

> >   Event generation register.

> > const uint32 RESERVED2

> >   Reserved.

> > const uint32 RESERVED3

> >   Reserved.

> > const uint32 RESERVED4

> >   Reserved.

> > __io uint32 CNT

> >   Counter.

> > __io uint32 PSC

> >   Prescaler.

> > __io uint32 ARR

> >   Auto-reload register.

timer_type enum

  Timer type.

  Type marker for timer_dev.

  See: | timer_dev

  Values:

  - `TIMER_ADVANCED` -

    Advanced type.

  - `TIMER_GENERAL` -

    General purpose type.

  - `TIMER_BASIC` -

    Basic type.

struct timer_dev

> Timer device type.

> Public Members

> > timer_reg_map regs

> >   Register map.

> > rcc_clk_id clk_id

> >   RCC clock information.

> > timer_type type

> >   Timer’s type.

> > voidFuncPtr handlers[]

> >   User IRQ handlers.

timer_mode enum

  Used to configure the behavior of a timer channel.

  Note that not all timers can be configured in every mode.

  Values:

  - `TIMER_DISABLED` -

    In this mode, the timer stops counting, channel interrupts are detached, and no state changes are output.

  - `TIMER_PWM` -

    PWM output mode.

    This is the default mode for pins after initialization.

  - `TIMER_OUTPUT_COMPARE` -

    In this mode, the timer counts from 0 to its reload value repeatedly; every time the counter value reaches one of the channel compare values, the corresponding interrupt is fired.

timer_channel enum

  Timer channel numbers.

  Values:

  - `TIMER_CH1``= 1` -

    Channel 1.

  - `TIMER_CH2``= 2` -

    Channel 2.

  - `TIMER_CH3``= 3` -

    Channel 3.

  - `TIMER_CH4``= 4` -

    Channel 4.

timer_interrupt_id enum

  Timer interrupt number.

  Not all timers support all of these values; see the descriptions for each value.

  Values:

  - `TIMER_UPDATE_INTERRUPT` -

    Update interrupt, available on all timers.

  - `TIMER_CC1_INTERRUPT` -

    Capture/compare 1 interrupt, available on general and advanced timers only.

  - `TIMER_CC2_INTERRUPT` -

    Capture/compare 2 interrupt, general and advanced timers only.

  - `TIMER_CC3_INTERRUPT` -

    Capture/compare 3 interrupt, general and advanced timers only.

  - `TIMER_CC4_INTERRUPT` -

    Capture/compare 4 interrupt, general and advanced timers only.

  - `TIMER_COM_INTERRUPT` -

    COM interrupt, advanced timers only.

  - `TIMER_TRG_INTERRUPT` -

    Trigger interrupt, general and advanced timers only.

  - `TIMER_BREAK_INTERRUPT` -

    Break interrupt, advanced timers only.

timer_dma_base_addr enum

  Timer DMA base address.

  Defines the base address for DMA transfers.

  Values:

  - `TIMER_DMA_BASE_CR1``= TIMER_DCR_DBA_CR1` -

    Base is control register 1.

  - `TIMER_DMA_BASE_CR2``= TIMER_DCR_DBA_CR2` -

    Base is control register 2.

  - `TIMER_DMA_BASE_SMCR``= TIMER_DCR_DBA_SMCR` -

    Base is slave mode control register.

  - `TIMER_DMA_BASE_DIER``= TIMER_DCR_DBA_DIER` -

    Base is DMA interrupt enable register.

  - `TIMER_DMA_BASE_SR``= TIMER_DCR_DBA_SR` -

    Base is status register.

  - `TIMER_DMA_BASE_EGR``= TIMER_DCR_DBA_EGR` -

    Base is event generation register.

  - `TIMER_DMA_BASE_CCMR1``= TIMER_DCR_DBA_CCMR1` -

    Base is capture/compare mode register 1.

  - `TIMER_DMA_BASE_CCMR2``= TIMER_DCR_DBA_CCMR2` -

    Base is capture/compare mode register 2.

  - `TIMER_DMA_BASE_CCER``= TIMER_DCR_DBA_CCER` -

    Base is capture/compare enable register.

  - `TIMER_DMA_BASE_CNT``= TIMER_DCR_DBA_CNT` -

    Base is counter.

  - `TIMER_DMA_BASE_PSC``= TIMER_DCR_DBA_PSC` -

    Base is prescaler.

  - `TIMER_DMA_BASE_ARR``= TIMER_DCR_DBA_ARR` -

    Base is auto-reload register.

  - `TIMER_DMA_BASE_RCR``= TIMER_DCR_DBA_RCR` -

    Base is repetition counter register.

  - `TIMER_DMA_BASE_CCR1``= TIMER_DCR_DBA_CCR1` -

    Base is capture/compare register 1.

  - `TIMER_DMA_BASE_CCR2``= TIMER_DCR_DBA_CCR2` -

    Base is capture/compare register 2.

  - `TIMER_DMA_BASE_CCR3``= TIMER_DCR_DBA_CCR3` -

    Base is capture/compare register 3.

  - `TIMER_DMA_BASE_CCR4``= TIMER_DCR_DBA_CCR4` -

    Base is capture/compare register 4.

  - `TIMER_DMA_BASE_BDTR``= TIMER_DCR_DBA_BDTR` -

    Base is break and dead-time register.

  - `TIMER_DMA_BASE_DCR``= TIMER_DCR_DBA_DCR` -

    Base is DMA control register.

  - `TIMER_DMA_BASE_DMAR``= TIMER_DCR_DBA_DMAR` -

    Base is DMA address for full transfer.

timer_oc_mode enum

  Timer output compare modes.

  Values:

  - `TIMER_OC_MODE_FROZEN``= 0 << 4` -

    Frozen: comparison between output compare register and counter has no effect on the outputs.

  - `TIMER_OC_MODE_ACTIVE_ON_MATCH``= 1 << 4` -

    OCxREF signal is forced high when the count matches the channel capture/compare register.

  - `TIMER_OC_MODE_INACTIVE_ON_MATCH``= 2 << 4` -

    OCxREF signal is forced low when the counter matches the channel capture/compare register.

  - `TIMER_OC_MODE_TOGGLE``= 3 << 4` -

    OCxREF toggles when counter matches the cannel capture/compare register.

  - `TIMER_OC_MODE_FORCE_INACTIVE``= 4 << 4` -

    OCxREF is forced low.

  - `TIMER_OC_MODE_FORCE_ACTIVE``= 5 << 4` -

    OCxREF is forced high.

  - `TIMER_OC_MODE_PWM_1``= 6 << 4` -

    PWM mode 1.

    In upcounting, channel is active as long as count is less than channel capture/compare register, else inactive. In downcounting, channel is inactive as long as count exceeds capture/compare register, else active.

  - `TIMER_OC_MODE_PWM_2``= 7 << 4` -

    PWM mode 2.

    In upcounting, channel is inactive as long as count is less than capture/compare register, else active. In downcounting, channel is active as long as count exceeds capture/compare register, else inactive.

timer_oc_mode_flags enum

  Timer output compare mode flags.

  See: | timer_oc_set_mode()

  Values:

  - `TIMER_OC_CE``= BIT(7)` -

    Output compare clear enable.

  - `TIMER_OC_PE``= BIT(3)` -

    Output compare preload enable.

  - `TIMER_OC_FE``= BIT(2)` -

    Output compare fast enable.

## Devices

timer_dev * TIMER1

  Timer 1 device (advanced).

timer_dev * TIMER2

  Timer 2 device (general-purpose).

timer_dev * TIMER3

  Timer 3 device (general-purpose).

timer_dev * TIMER4

  Timer 4 device (general-purpose).

timer_dev * TIMER5

  Timer 5 device (general-purpose).

timer_dev * TIMER6

  Timer 6 device (basic).

timer_dev * TIMER7

  Timer 7 device (basic).

timer_dev * TIMER8

  Timer 8 device (advanced).

## Functions

### Enabling and Disabling

void timer_init(timer_dev * dev)

  Initialize a timer, and reset its register map.

  Parameters: | `dev` - Timer to initialize

void timer_init_all(void)

  Initialize all timer devices on the chip.

void timer_disable(timer_dev * dev)

  Disable a timer.

  The timer will stop counting, all DMA requests and interrupts will be disabled, and no state changes will be output.

  Parameters: | `dev` - Timer to disable.

void timer_disable_all(void)

  Disables all timers on the device.

### General Configuration

void timer_set_mode(timer_dev * dev, uint8 channel, timer_mode mode)

  Sets the mode of an individual timer channel.

  Note that not all timers can be configured in every mode. For example, basic timers cannot be configured to output compare mode. Be sure to use a timer which is appropriate for the mode you want.

  Parameters: | `dev` - Timer whose channel mode to set `channel` - Relevant channel `mode` - New timer mode for channel

void timer_foreach(void(*)( timer_dev *) fn)

  Call a function on timer devices.

  Parameters: | `fn` - Function to call on each timer device.

### Count and Prescaler

uint16 timer_get_count(timer_dev * dev)

  Returns the timer’s counter value.

  This value is likely to be inaccurate if the counter is running with a low prescaler.

  Parameters: | `dev` - Timer whose counter to return

void timer_set_count(timer_dev * dev, uint16 value)

  Sets the counter value for the given timer.

  Parameters: | `dev` - Timer whose counter to set `value` - New counter value

void timer_pause(timer_dev * dev)

  Stop a timer’s counter from changing.

  Does not affect the timer’s mode or other settings.

  Parameters: | `dev` - Device whose counter to pause.

void timer_resume(timer_dev * dev)

  Start a timer’s counter.

  Does not affect the timer’s mode or other settings.

  Parameters: | `dev` - Device whose counter to resume

void timer_generate_update(timer_dev * dev)

  Generate an update event for the given timer.

  Normally, this will cause the prescaler and auto-reload values in the PSC and ARR registers to take immediate effect. However, this function will do nothing if the UDIS bit is set in the timer’s CR1 register (UDIS is cleared by default).

  Parameters: | `dev` - Timer device to generate an update for.

uint16 timer_get_prescaler(timer_dev * dev)

  Returns the given timer’s prescaler.

  Note that if the timer’s prescaler is set (e.g. via timer_set_prescaler() or accessing a TIMx_PSC register), the value returned by this function will reflect the new setting, but the timer’s counter will only reflect the new prescaler at the next update event.

  Parameters: | `dev` - Timer whose prescaler to return
  See: | timer_generate_update()

void timer_set_prescaler(timer_dev * dev, uint16 psc)

  Set a timer’s prescale value.

  The new value will not take effect until the next update event.

  Parameters: | `dev` - Timer whose prescaler to set `psc` - New prescaler value
  See: | timer_generate_update()

uint16 timer_get_reload(timer_dev * dev)

  Returns a timer’s reload value.

  Parameters: | `dev` - Timer whose reload value to return

void timer_set_reload(timer_dev * dev, uint16 arr)

  Set a timer’s reload value.

  Parameters: | `dev` - Timer whose reload value to set `arr` - New reload value to use. Takes effect at next update event.
  See: | timer_generate_update()

### Interrupts

void timer_attach_interrupt(timer_dev * dev, uint8 interrupt, voidFuncPtr handler)

  Attach a timer interrupt.

  Parameters: | `dev` - Timer device `interrupt` - Interrupt number to attach to; this may be any timer_interrupt_id or timer_channel value appropriate for the timer. `handler` - Handler to attach to the given interrupt.
  See: | timer_interrupt_id timer_channel

void timer_detach_interrupt(timer_dev * dev, uint8 interrupt)

  Detach a timer interrupt.

  Parameters: | `dev` - Timer device `interrupt` - Interrupt number to detach; this may be any timer_interrupt_id or timer_channel value appropriate for the timer.
  See: | timer_interrupt_id timer_channel

void timer_enable_irq(timer_dev * dev, uint8 interrupt)

  Enable a timer interrupt.

  Parameters: | `dev` - Timer device. `interrupt` - Interrupt number to enable; this may be any timer_interrupt_id value appropriate for the timer.
  See: | timer_interrupt_id timer_channel

void timer_disable_irq(timer_dev * dev, uint8 interrupt)

  Disable a timer interrupt.

  Parameters: | `dev` - Timer device. `interrupt` - Interrupt number to disable; this may be any timer_interrupt_id value appropriate for the timer.
  See: | timer_interrupt_id timer_channel

### Capture/Compare

uint16 timer_get_compare(timer_dev * dev, uint8 channel)

  Get the compare value for the given timer channel.

  Parameters: | `dev` - Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL. `channel` - Channel whose compare value to get.

void timer_set_compare(timer_dev * dev, uint8 channel, uint16 value)

  Set the compare value for the given timer channel.

  Parameters: | `dev` - Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL. `channel` - Channel whose compare value to set. `value` - New compare value.

void timer_cc_enable(timer_dev * dev, uint8 channel)

  Enable a timer channel’s capture/compare signal.

  If the channel is configured as output, the corresponding output compare signal will be output on the corresponding output pin. If the channel is configured as input, enables capture of the counter value into the input capture/compare register.

  Parameters: | `dev` - Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL. `channel` - Channel to enable, from 1 to 4.

void timer_cc_disable(timer_dev * dev, uint8 channel)

  Disable a timer channel’s output compare or input capture signal.

  Parameters: | `dev` - Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL. `channel` - Channel to disable, from 1 to 4.
  See: | timer_cc_enable()

uint8 timer_cc_get_pol(timer_dev * dev, uint8 channel)

  Get a channel’s capture/compare output polarity.

  Parameters: | `dev` - Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL. `channel` - Channel whose capture/compare output polarity to get.
  Return: | Polarity, either 0 or 1.
  See: | timer_cc_set_polarity()

void timer_cc_set_pol(timer_dev * dev, uint8 channel, uint8 pol)

  Set a timer channel’s capture/compare output polarity.

  If the timer channel is configured as output: polarity == 0 means the output channel will be active high; polarity == 1 means active low.

  If the timer channel is configured as input: polarity == 0 means capture is done on the rising edge of ICn; when used as an external trigger, ICn is non-inverted. polarity == 1 means capture is done on the falling edge of ICn; when used as an external trigger, ICn is inverted.

  Parameters: | `dev` - Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL. `channel` - Channel whose capture/compare output polarity to set. `pol` - New polarity, 0 or 1.

void timer_oc_set_mode(timer_dev * dev, uint8 channel, timer_oc_mode mode, uint8 flags)

  Configure a channel’s output compare mode.

  Parameters: | `dev` - Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL. `channel` - Channel to configure in output compare mode. `mode` - Timer mode to set. `flags` - OR of timer_oc_mode_flags.
  See: | timer_oc_mode timer_oc_mode_flags

### DMA

void timer_dma_enable_trg_req(timer_dev * dev)

  Enable a timer’s trigger DMA request.

  Parameters: | `dev` - Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL

void timer_dma_disable_trg_req(timer_dev * dev)

  Disable a timer’s trigger DMA request.

  Parameters: | `dev` - Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL

void timer_dma_enable_req(timer_dev * dev, uint8 channel)

  Enable a timer channel’s DMA request.

  Parameters: | `dev` - Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL `channel` - Channel whose DMA request to enable.

uint8 timer_dma_get_burst_len(timer_dev * dev)

  Get a timer’s DMA burst length.

  Parameters: | `dev` - Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL.
  Return: | Number of bytes to be transferred per DMA request, from 1 to 18.

void timer_dma_set_burst_len(timer_dev * dev, uint8 length)

  Set a timer’s DMA burst length.

  Parameters: | `dev` - Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL. `length` - DMA burst length; i.e., number of bytes to transfer per DMA request, from 1 to 18.

timer_dma_base_addr timer_dma_get_base_addr(timer_dev * dev)

  Get the timer’s DMA base address.

  Some restrictions apply; see ST RM0008.

  Parameters: | `dev` - Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL.
  Return: | DMA base address

void timer_dma_set_base_addr(timer_dev * dev, timer_dma_base_addr dma_base)

  Set the timer’s DMA base address.

  Some restrictions apply; see ST RM0008.

  Parameters: | `dev` - Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL. `dma_base` - DMA base address.

## Register Map Base Pointers

TIMER1_BASE

  Timer 1 register map base pointer.

TIMER2_BASE

  Timer 2 register map base pointer.

TIMER3_BASE

  Timer 3 register map base pointer.

TIMER4_BASE

  Timer 4 register map base pointer.

TIMER5_BASE

  Timer 5 register map base pointer.

TIMER6_BASE

  Timer 6 register map base pointer.

TIMER7_BASE

  Timer 7 register map base pointer.

TIMER8_BASE

  Timer 8 register map base pointer.

## Register Bit Definitions

### Control register 1 (CR1)

TIMER_CR1_ARPE_BIT

TIMER_CR1_DIR_BIT

TIMER_CR1_OPM_BIT

TIMER_CR1_URS_BIT

TIMER_CR1_UDIS_BIT

TIMER_CR1_CEN_BIT

TIMER_CR1_CKD

TIMER_CR1_CKD_1TCKINT

TIMER_CR1_CKD_2TCKINT

TIMER_CR1_CKD_4TICKINT

TIMER_CR1_ARPE

TIMER_CR1_CKD_CMS

TIMER_CR1_CKD_CMS_EDGE

TIMER_CR1_CKD_CMS_CENTER1

TIMER_CR1_CKD_CMS_CENTER2

TIMER_CR1_CKD_CMS_CENTER3

TIMER_CR1_DIR

TIMER_CR1_OPM

TIMER_CR1_URS

TIMER_CR1_UDIS

TIMER_CR1_CEN

### Control register 2 (CR2)

TIMER_CR2_OIS4_BIT

TIMER_CR2_OIS3N_BIT

TIMER_CR2_OIS3_BIT

TIMER_CR2_OIS2N_BIT

TIMER_CR2_OIS2_BIT

TIMER_CR2_OIS1N_BIT

TIMER_CR2_OIS1_BIT

TIMER_CR2_TI1S_BIT

TIMER_CR2_CCDS_BIT

TIMER_CR2_CCUS_BIT

TIMER_CR2_CCPC_BIT

TIMER_CR2_OIS4

TIMER_CR2_OIS3N

TIMER_CR2_OIS3

TIMER_CR2_OIS2N

TIMER_CR2_OIS2

TIMER_CR2_OIS1N

TIMER_CR2_OIS1

TIMER_CR2_TI1S

TIMER_CR2_MMS

TIMER_CR2_MMS_RESET

TIMER_CR2_MMS_ENABLE

TIMER_CR2_MMS_UPDATE

TIMER_CR2_MMS_COMPARE_PULSE

TIMER_CR2_MMS_COMPARE_OC1REF

TIMER_CR2_MMS_COMPARE_OC2REF

TIMER_CR2_MMS_COMPARE_OC3REF

TIMER_CR2_MMS_COMPARE_OC4REF

TIMER_CR2_CCDS

TIMER_CR2_CCUS

TIMER_CR2_CCPC

### Slave mode control register (SMCR)

TIMER_SMCR_ETP_BIT

TIMER_SMCR_ECE_BIT

TIMER_SMCR_MSM_BIT

TIMER_SMCR_ETP

TIMER_SMCR_ECE

TIMER_SMCR_ETPS

TIMER_SMCR_ETPS_OFF

TIMER_SMCR_ETPS_DIV2

TIMER_SMCR_ETPS_DIV4

TIMER_SMCR_ETPS_DIV8

TIMER_SMCR_ETF

TIMER_SMCR_MSM

TIMER_SMCR_TS

TIMER_SMCR_TS_ITR0

TIMER_SMCR_TS_ITR1

TIMER_SMCR_TS_ITR2

TIMER_SMCR_TS_ITR3

TIMER_SMCR_TS_TI1F_ED

TIMER_SMCR_TS_TI1FP1

TIMER_SMCR_TS_TI2FP2

TIMER_SMCR_TS_ETRF

TIMER_SMCR_SMS

TIMER_SMCR_SMS_DISABLED

TIMER_SMCR_SMS_ENCODER1

TIMER_SMCR_SMS_ENCODER2

TIMER_SMCR_SMS_ENCODER3

TIMER_SMCR_SMS_RESET

TIMER_SMCR_SMS_GATED

TIMER_SMCR_SMS_TRIGGER

TIMER_SMCR_SMS_EXTERNAL

### DMA/Interrupt enable register (DIER)

TIMER_DIER_TDE_BIT

TIMER_DIER_CC4DE_BIT

TIMER_DIER_CC3DE_BIT

TIMER_DIER_CC2DE_BIT

TIMER_DIER_CC1DE_BIT

TIMER_DIER_UDE_BIT

TIMER_DIER_TIE_BIT

TIMER_DIER_CC4IE_BIT

TIMER_DIER_CC3IE_BIT

TIMER_DIER_CC2IE_BIT

TIMER_DIER_CC1IE_BIT

TIMER_DIER_UIE_BIT

TIMER_DIER_TDE

TIMER_DIER_CC4DE

TIMER_DIER_CC3DE

TIMER_DIER_CC2DE

TIMER_DIER_CC1DE

TIMER_DIER_UDE

TIMER_DIER_TIE

TIMER_DIER_CC4IE

TIMER_DIER_CC3IE

TIMER_DIER_CC2IE

TIMER_DIER_CC1IE

TIMER_DIER_UIE

### Status register (SR)

TIMER_SR_CC4OF_BIT

TIMER_SR_CC3OF_BIT

TIMER_SR_CC2OF_BIT

TIMER_SR_CC1OF_BIT

TIMER_SR_BIF_BIT

TIMER_SR_TIF_BIT

TIMER_SR_COMIF_BIT

TIMER_SR_CC4IF_BIT

TIMER_SR_CC3IF_BIT

TIMER_SR_CC2IF_BIT

TIMER_SR_CC1IF_BIT

TIMER_SR_UIF_BIT

TIMER_SR_CC4OF

TIMER_SR_CC3OF

TIMER_SR_CC2OF

TIMER_SR_CC1OF

TIMER_SR_BIF

TIMER_SR_TIF

TIMER_SR_COMIF

TIMER_SR_CC4IF

TIMER_SR_CC3IF

TIMER_SR_CC2IF

TIMER_SR_CC1IF

TIMER_SR_UIF

### Event generation register (EGR)

TIMER_EGR_TG_BIT

TIMER_EGR_CC4G_BIT

TIMER_EGR_CC3G_BIT

TIMER_EGR_CC2G_BIT

TIMER_EGR_CC1G_BIT

TIMER_EGR_UG_BIT

TIMER_EGR_TG

TIMER_EGR_CC4G

TIMER_EGR_CC3G

TIMER_EGR_CC2G

TIMER_EGR_CC1G

TIMER_EGR_UG

### Capture/compare mode registers, common values

TIMER_CCMR_CCS_OUTPUT

TIMER_CCMR_CCS_INPUT_TI1

TIMER_CCMR_CCS_INPUT_TI2

TIMER_CCMR_CCS_INPUT_TRC

### Capture/compare mode register 1 (CCMR1)

TIMER_CCMR1_OC2CE_BIT

TIMER_CCMR1_OC2PE_BIT

TIMER_CCMR1_OC2FE_BIT

TIMER_CCMR1_OC1CE_BIT

TIMER_CCMR1_OC1PE_BIT

TIMER_CCMR1_OC1FE_BIT

TIMER_CCMR1_OC2CE

TIMER_CCMR1_OC2M

TIMER_CCMR1_IC2F

TIMER_CCMR1_OC2PE

TIMER_CCMR1_OC2FE

TIMER_CCMR1_IC2PSC

TIMER_CCMR1_CC2S

TIMER_CCMR1_CC2S_OUTPUT

TIMER_CCMR1_CC2S_INPUT_TI1

TIMER_CCMR1_CC2S_INPUT_TI2

TIMER_CCMR1_CC2S_INPUT_TRC

TIMER_CCMR1_OC1CE

TIMER_CCMR1_OC1M

TIMER_CCMR1_IC1F

TIMER_CCMR1_OC1PE

TIMER_CCMR1_OC1FE

TIMER_CCMR1_IC1PSC

TIMER_CCMR1_CC1S

TIMER_CCMR1_CC1S_OUTPUT

TIMER_CCMR1_CC1S_INPUT_TI1

TIMER_CCMR1_CC1S_INPUT_TI2

TIMER_CCMR1_CC1S_INPUT_TRC

### Capture/compare mode register 2 (CCMR2)

TIMER_CCMR2_OC4CE_BIT

TIMER_CCMR2_OC4PE_BIT

TIMER_CCMR2_OC4FE_BIT

TIMER_CCMR2_OC3CE_BIT

TIMER_CCMR2_OC3PE_BIT

TIMER_CCMR2_OC3FE_BIT

TIMER_CCMR2_OC4CE

TIMER_CCMR2_OC4M

TIMER_CCMR2_IC2F

TIMER_CCMR2_OC4PE

TIMER_CCMR2_OC4FE

TIMER_CCMR2_IC2PSC

TIMER_CCMR2_CC4S

TIMER_CCMR1_CC4S_OUTPUT

TIMER_CCMR1_CC4S_INPUT_TI1

TIMER_CCMR1_CC4S_INPUT_TI2

TIMER_CCMR1_CC4S_INPUT_TRC

TIMER_CCMR2_OC3CE

TIMER_CCMR2_OC3M

TIMER_CCMR2_IC1F

TIMER_CCMR2_OC3PE

TIMER_CCMR2_OC3FE

TIMER_CCMR2_IC1PSC

TIMER_CCMR2_CC3S

TIMER_CCMR1_CC3S_OUTPUT

TIMER_CCMR1_CC3S_INPUT_TI1

TIMER_CCMR1_CC3S_INPUT_TI2

TIMER_CCMR1_CC3S_INPUT_TRC

### Capture/compare enable register (CCER)

TIMER_CCER_CC4P_BIT

TIMER_CCER_CC4E_BIT

TIMER_CCER_CC3P_BIT

TIMER_CCER_CC3E_BIT

TIMER_CCER_CC2P_BIT

TIMER_CCER_CC2E_BIT

TIMER_CCER_CC1P_BIT

TIMER_CCER_CC1E_BIT

TIMER_CCER_CC4P

TIMER_CCER_CC4E

TIMER_CCER_CC3P

TIMER_CCER_CC3E

TIMER_CCER_CC2P

TIMER_CCER_CC2E

TIMER_CCER_CC1P

TIMER_CCER_CC1E

### Break and dead-time register (BDTR)

TIMER_BDTR_MOE_BIT

TIMER_BDTR_AOE_BIT

TIMER_BDTR_BKP_BIT

TIMER_BDTR_BKE_BIT

TIMER_BDTR_OSSR_BIT

TIMER_BDTR_OSSI_BIT

TIMER_BDTR_MOE

TIMER_BDTR_AOE

TIMER_BDTR_BKP

TIMER_BDTR_BKE

TIMER_BDTR_OSSR

TIMER_BDTR_OSSI

TIMER_BDTR_LOCK

TIMER_BDTR_LOCK_OFF

TIMER_BDTR_LOCK_LEVEL1

TIMER_BDTR_LOCK_LEVEL2

TIMER_BDTR_LOCK_LEVEL3

TIMER_BDTR_DTG

### DMA control register (DCR)

TIMER_DCR_DBL

TIMER_DCR_DBL_1BYTE

TIMER_DCR_DBL_2BYTE

TIMER_DCR_DBL_3BYTE

TIMER_DCR_DBL_4BYTE

TIMER_DCR_DBL_5BYTE

TIMER_DCR_DBL_6BYTE

TIMER_DCR_DBL_7BYTE

TIMER_DCR_DBL_8BYTE

TIMER_DCR_DBL_9BYTE

TIMER_DCR_DBL_10BYTE

TIMER_DCR_DBL_11BYTE

TIMER_DCR_DBL_12BYTE

TIMER_DCR_DBL_13BYTE

TIMER_DCR_DBL_14BYTE

TIMER_DCR_DBL_15BYTE

TIMER_DCR_DBL_16BYTE

TIMER_DCR_DBL_17BYTE

TIMER_DCR_DBL_18BYTE

TIMER_DCR_DBA

TIMER_DCR_DBA_CR1

TIMER_DCR_DBA_CR2

TIMER_DCR_DBA_SMCR

TIMER_DCR_DBA_DIER

TIMER_DCR_DBA_SR

TIMER_DCR_DBA_EGR

TIMER_DCR_DBA_CCMR1

TIMER_DCR_DBA_CCMR2

TIMER_DCR_DBA_CCER

TIMER_DCR_DBA_CNT

TIMER_DCR_DBA_PSC

TIMER_DCR_DBA_ARR

TIMER_DCR_DBA_RCR

TIMER_DCR_DBA_CCR1

TIMER_DCR_DBA_CCR2

TIMER_DCR_DBA_CCR3

TIMER_DCR_DBA_CCR4

TIMER_DCR_DBA_BDTR

TIMER_DCR_DBA_DCR

TIMER_DCR_DBA_DMAR

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