General Purpose Input/Output (GPIO) port and Alternate Function Input/Output (AFIO) support.
GPIO register map type.
Public Members
- __io uint32 CRL
Port configuration register low.
- __io uint32 CRH
Port configuration register high.
- __io uint32 IDR
Port input data register.
- __io uint32 ODR
Port output data register.
- __io uint32 BSRR
Port bit set/reset register.
- __io uint32 BRR
Port bit reset register.
- __io uint32 LCKR
Port configuration lock register.
GPIO device type.
Public Members
- gpio_reg_map * regs
Register map.
- rcc_clk_id clk_id
RCC clock information.
- afio_exti_port exti_port
AFIO external interrupt port value.
GPIO Pin modes.
These only allow for 50MHZ max output speeds; if you want slower, use direct register access.
Values:
Output push-pull.
Output open-drain.
Alternate function output push-pull.
Alternate function output open drain.
Analog input.
Input floating.
Input pull-down.
Input pull-up.
AFIO register map.
Public Members
- __io uint32 EVCR
Event control register.
- __io uint32 MAPR
AF remap and debug I/O configuration register.
- __io uint32 EXTICR1
External interrupt configuration register 1.
- __io uint32 EXTICR2
External interrupt configuration register 2.
- __io uint32 EXTICR3
External interrupt configuration register 3.
- __io uint32 EXTICR4
External interrupt configuration register 4.
- __io uint32 MAPR2
AF remap and debug I/O configuration register 2.
External interrupt line port selector.
Used to determine which GPIO port to map an external interrupt line onto.
Values:
Use port A (PAx) pin.
Use port B (PBx) pin.
Use port C (PCx) pin.
Use port D (PDx) pin.
Use port E (PEx) pin.
Use port F (PFx) pin.
Use port G (PGx) pin.
External interrupt line numbers.
Values:
External interrupt line 0.
External interrupt line 1.
External interrupt line 2.
External interrupt line 3.
External interrupt line 4.
External interrupt line 5.
External interrupt line 6.
External interrupt line 7.
External interrupt line 8.
External interrupt line 9.
External interrupt line 10.
External interrupt line 11.
External interrupt line 12.
External interrupt line 13.
External interrupt line 14.
External interrupt line 15.
Available peripheral remaps.
See: | afio_remap() |
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Values:
ADC 2 external trigger regular conversion remapping.
ADC 2 external trigger injected conversion remapping.
ADC 1 external trigger regular conversion remapping.
ADC 1 external trigger injected conversion remapping.
Timer 5 channel 4 internal remapping.
Port D0/Port D1 mapping on OSC_IN/OSC_OUT.
CAN alternate function remapping 1 (RX on PB8, TX on PB9)
CAN alternate function remapping 2 (RX on PD0, TX on PD1)
Timer 4 remapping.
Timer 3 partial remapping.
Timer 3 full remapping.
Timer 2 partial remapping 1 (CH1 and ETR on PA15, CH2 on PB3, CH3 on PA2, CH4 on PA3)
Timer 2 partial remapping 2 (CH1 and ETR on PA0, CH2 on PA1, CH3 on PB10, CH4 on PB11)
Timer 2 full remapping.
USART 2 remapping.
USART 1 remapping.
I2C 1 remapping.
SPI 1 remapping.
NADV signal not connected.
Timer 14 remapping.
Timer 13 remapping.
Timer 11 remapping.
Timer 10 remapping.
Timer 9.
Debug port configuration.
Used to configure the behavior of JTAG and Serial Wire (SW) debug ports and their associated GPIO pins.
See: | afio_cfg_debug_ports() |
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Values:
Full Serial Wire and JTAG debug.
Full Serial Wire and JTAG, but no NJTRST.
Serial Wire debug only (JTAG-DP disabled, SW-DP enabled)
No debug; all JTAG and SW pins are free for use as GPIOs.
GPIO port A device.
GPIO port B device.
GPIO port C device.
GPIO port D device.
GPIO port E device.
GPIO port F device.
GPIO port G device.
Initialize a GPIO device.
Enables the clock for and resets the given device.
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Initialize and reset all available GPIO devices.
Set the mode of a GPIO pin.
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See: |
Get a GPIO port’s corresponding afio_exti_port.
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Set or reset a GPIO pin.
Pin must have previously been configured to output mode.
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Determine whether or not a GPIO pin is set.
Pin must have previously been configured to input mode.
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Return: | True if the pin is set, false otherwise. |
Toggle a pin configured as output push-pull.
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Initialize the AFIO clock, and reset the AFIO registers.
Select a source input for an external interrupt.
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See: |
Perform an alternate function remap.
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Enable or disable the JTAG and SW debug ports.
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See: |
GPIO port A register map base pointer.
GPIO port B register map base pointer.
GPIO port C register map base pointer.
GPIO port D register map base pointer.
GPIO port E register map base pointer.
GPIO port F register map base pointer.
GPIO port G register map base pointer.
AFIO register map base pointer.
These values apply to both the low and high configuration registers (ST RM0008: GPIOx_CRL and GPIOx_CRH). You can shift them right by the appropriate number of bits for the GPIO port bit you’re interested in to obtain a bit mask.
For example, to mask out just the value of GPIOA_CRH_CNF12, note that GPIO port bit 12’s configuration starts at bit 18 in the corresponding CRH. Thus, an appropriate mask is GPIOA_BASE->CRH & (GPIO_CR_CNF << 18).